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rev: 1.03 11/2000 1/13 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs 71 024 t/u 64k x 24 1.5 mb asynchronous sram 8, 10, 12, 15 ns 3.3 v v dd tqfp, fpbga commercial temp industrial temp features ? fast access time: 8, 10, 12, 15 ns ? cmos low power operation: 190/160/130/110 ma at minimum cycle time. ? single 3.3 v 0.3 v power supply ? all inputs and outputs are ttl-compatible ? fully static operation ? industrial temperature option: ?40 to 85c ? package t: 100-pin tqfp package u: 6 mm x 8 mm fine pitch ball grid array description the gs 71 024 is a high speed cmos static ram organized as 65,536 words by 24 bits. static design eliminates the need for external clocks or timing strobes. the gs71024 operates on a single 3.3 v power supply, and all inputs and outputs are ttl- compatible. the gs 71 024 is available in a 6 mm x 8 mm fine pitch bga package, as well as in a 100-pin tqfp package. fine pitch bga bump configuration 6 mm x 8 mm, 0.75 mm bump pitch top view block diagram 1 2 3 4 5 6 a dq a 3 a 2 a 1 a 0 dq b dq dq ce2 we dq dq c dq dq ce1 oe dq dq d v ss dq a 5 a 4 dq v dd e v dd dq a 7 a 6 dq v ss f dq dq a 9 a 8 dq dq g dq dq a 11 a 10 dq dq h dq a 15 a 14 a 13 a 12 dq pin descriptions symbol description symbol description a 0 to a 15 address input dq 1 to dq 24 data input/output x/ y vector input v/ s address multiplexer control we write enable input oe output enable input ce1 , ce2 chip enable input ? ? v dd +3.3 v power supply v ss ground memory array 1024 x 1536 row decoder column decoder address input control i/o buffer a 0 a 15 ce1 we oe dq 1 dq 24 0 1 q a 14 x/ y v/ s ce2
rev: 1.03 11/2000 2/13 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs 71 024 t/u 100-pin tqfp pinout nc nc nc nc nc dq 12 dq 11 dq 10 dq 9 v ss v dd dq 8 dq 7 v ss nc v dd nc dq 6 dq 5 v dd v ss dq 4 dq 3 dq 2 dq 1 nc nc nc nc nc n c a 1 3 a 1 2 a 1 1 a 1 0 a 9 a 8 n c n c v s s v d d n c n c a 7 a 6 a 5 a 4 a 3 n c a 1 4 a 1 5 c e 1 n c n c n c w e n c v d d v s s o e n c n c n c a 0 a 1 a 2 top view nc nc dq 15 dq 16 v ss v dd dq 17 dq 18 nc v dd nc v ss dq 19 dq 20 v dd v ss dq 21 dq 22 dq 23 nc nc nc nc dq 13 d q 24 nc nc nc dq 14 nc 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 v / s c e 2 n c x / y
rev: 1.03 11/2000 3/13 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs 71 024 t/u x: ?h? or ?l? note: permanent device damage may occur if absolute maximum ratings are exceeded. functional operation shall be restricted to rec- ommended operating conditions. exposure to higher than recommended voltages for extended periods of time could affect device reliability. truth table ce1 ce2 oe we v/ s mode dq0 to dq23 v dd current h x x x x not selected high z isb1, isb2 x l x x x not selected high z l h l h h read using x/ y data out i dd l h l h l read using a15 data out l h x l h write using x/ y data in l h x l l write using a15 data in l h h h x output disable high z absolute maximum ratings parameter symbol rating unit supply voltage v dd ?0.5 to +4.6 v input voltage v in ?0.5 to v dd + 0.5 ( 4.6 v max.) v output voltage v out ?0.5 to v dd + 0.5 ( 4.6 v max.) v allowable tqfp power dissipation pd 1 w allowable fpbga power dissipation pd 1 w storage temperature t stg ?55 to 150 o c
rev: 1.03 11/2000 4/13 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs 71 024 t/u notes: 1. input overshoot voltage should be less than v dd + 2 v and not exceed 20 ns. 2. input undershoot voltage should be greater than ?2 v and not exceed 20 ns. notes: 1. tested at t a = 25c, f = 1 mhz 2. these parameters are sampled and are not 100% tested recommended operating conditions parameter symbol minimum typical maximum unit supply voltage for -10/12/15 v dd 3.0 3.3 3.6 v supply voltage for -8 v dd 3.135 3.3 3.6 v input high voltage v ih 2.0 ? v dd + 0.3 v input low voltage v il ?0.3 ? 0.8 v ambient temperature, commercial range t ac 0 ? 70 o c ambient temperature, industrial range t ai ?40 ? 85 o c capacitance parameter symbol test condition maximum unit input capacitance c in v in = 0 v 5 pf i/o capacitance c out v out = 0 v 7 pf dc i/o pin characteristics parameter symbol test conditions minimum maximum input leakage current i il v in = 0 to v dd ?1ua 1ua output leakage current i ol output high z, v out = 0 to v dd ?1ua 1ua output high voltage v oh i oh = ?4ma 2.4 ? output low voltage v ol i ol = +4ma ? 0.4 v
rev: 1.03 11/2000 5/13 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs 71 024 t/u ac test conditions power supply currents parameter symbol test conditions 0 to 70c -40 to 85c 8 ns 10 ns 12 ns 15 ns 10 ns 12 ns 15 ns operating supply current i dd ce v il all other inputs 3 v ih or v il min. cycle time i out = 0 ma 190 ma 160 ma 130 ma 110 ma 165 ma 135 ma 115 ma standby current i sb1 ce 3 v ih all other inputs 3 v ih or v il min. cycle time 45 ma 40 ma 35 ma 30 ma 45 ma 40 ma 35 ma standby current i sb2 ce 3 v dd ? 0.2 v all other inputs 3 v dd ? 0.2 v or 0.2 v 10 ma 15 ma dq vt = 1.4 v 50 w 30pf 1 dq 3.3 v output load 1 output load 2 589 w 434 w 5pf 1 notes: 1. include scope and jig capacitance. 2. test conditions as specified with output loading as shown in fig. 1 unless otherwise noted 3. output load 2 for t lz , t hz , t olz and t ohz . parameter conditions input high level v ih = 2.4 v input low level v il = 0.4 v input rise time tr = 1 v/ns input fall time tf = 1 v/ns input reference level 1.4 v output reference level 1.4 v output load fig. 1& 2
rev: 1.03 11/2000 6/13 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs 71 024 t/u ac characteristics * these parameters are sampled and are not 100% tested read cycle parameter symbol -8 -10 -12 -15 unit min max min max min max min max read cycle time t rc 8 ? 10 ? 12 ? 15 ? ns address access time t aa ? 8 ? 10 ? 12 ? 15 ns chip enable access time ( ce1 , ce2) t ac ? 8 ? 10 ? 12 ? 15 ns mux control to output valid (v/ s ) t av ? 8 ? 10 ? 12 ? 15 ns output enable to output valid ( oe ) t oe ? 4 ? 5 ? 6 ? 7 ns output hold from address change t oh 3 ? 3 ? 3 ? 3 ? ns output hold from mux controls change t oh1 3 ? 3 ? 3 ? 3 ? ns chip enable to output in low z ( ce1 , ce2) t lz * 3 ? 3 ? 3 ? 3 ? ns output enable to output in low z ( oe ) t olz * 0 ? 0 ? 0 ? 0 ? ns chip disable to output in high z ( ce1 , ce2) t hz * ? 4 ? 5 ? 6 ? 7 ns output disable to output in high z ( oe ) t ohz * ? 4 ? 5 ? 6 ? 7 ns
rev: 1.03 11/2000 7/13 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs 71 024 t/u read cycle 1: ce = oe = v il , we = v ih read cycle 2: we = v ih t aa t oh t rc address data out previous data data valid t oh1 t av v/ s t aa t rc address t ac t lz t av t oe t olz ce1 (*1) v/ s oe data out t hz t ohz data valid high impedance *1 ce1 represents both ce1 low and ce2 high.
rev: 1.03 11/2000 8/13 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs 71 024 t/u * these parameters are sampled and are not 100% tested write cycle parameter symbol -8 -10 -12 -15 unit min max min max min max min max write cycle time t wc 8 ? 10 ? 12 ? 15 ? ns address valid to end of write t aw 5.5 ? 7 ? 8 ? 10 ? ns chip enable to end of write ( ce1 , ce2) t cw 5.5 ? 7 ? 8 ? 10 ? ns mux control to end of write (v/ s ) t vw 5.5 ? 7 ? 8 ? 10 ? ns data set up time t dw 4 ? 5 ? 6 ? 7 ? ns data hold time t dh 0 ? 0 ? 0 ? 0 ? ns write pulse width t wp 5.5 ? 7 ? 8 ? 10 ? ns address set up time t as 0 ? 0 ? 0 ? 0 ? ns mux control set up time t vs 0 ? 0 ? 0 ? 0 ? ns write recovery time ( we ) t wr 0 ? 0 ? 0 ? 0 ? ns write recovery time ( v/ s , ce1 , ce2 ) t wr1 0 ? 0 ? 0 ? 0 ? ns output low z from end of write t wlz * 2 ? 3 ? 3 ? 3 ? ns write to output in high z t whz * ? 4 ? 5 ? 6 ? 7 ns
rev: 1.03 11/2000 9/13 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs 71 024 t/u write cycle 1: we control write cycle 2: ce control t wc address ce1 (*1) v/ s we data in oe data out t aw t cw t vw t as t wp t wr t dw t dh t wlz t whz data valid high impedance (*2) (*3) (*3) t vs *1 ce1 represents both ce1 low and ce2 high. *2 write is executed when both ce1 and we are at low simultaneously. *3 do not apply the data input voltage to the output while dq pin is in output condition. t wc address ce1 (*1) v/ s we data in oe data out t aw t wp t as t cw t wr1 t dw t dh data valid high impedance t vw *1 ce1 represents both ce1 low and ce2 high.
rev: 1.03 11/2000 10/13 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs 71 024 t/u 6 mm x 8 mm fine pitch bga c 5 . 2 5 0 . 7 5 ( t y p ) . 3 . 7 5 p i n a 1 i n d e x 6 5 4 3 2 1 a b d e f g h 0 . 2 2 0 . 0 5 1 . 2 0 ( m a x ) 0 . 3 6 ( t y p ) b a l l d i a . 0 . 3 5 p i t c h 0 . 7 5 d 0.10 p i n a 1 i n d e x b o t t o m v i e w t o p v i e w 6 . 0 0 0 . 1 0 8 . 0 0 0 . 1 0 u n i t s : m m
rev: 1.03 11/2000 11/13 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs 71 024 t/u tqfp package drawing bpr 1999.05.18 d 1 d e1 e p i n 1 b e c l l1 a2 a1 y q notes: 1. all dimensions are in millimeters (mm). 2. package width and length do not include mold protrusion symbol description min. nom. max a1 standoff 0.05 0.10 0.15 a2 body thickness 1.35 1.40 1.45 b lead width 0.20 0.30 0.40 c lead thickness 0.09 0.20 d terminal dimension 21.9 22.0 22.1 d1 package body 19.9 20.0 20.1 e terminal dimension 15.9 16.0 16.1 e1 package body 13.9 14.0 14.1 e lead pitch 0.65 l foot length 0.45 0.60 0.75 l1 lead length 1.00 y coplanarity 0.10 q lead angle 0 7
rev: 1.03 11/2000 12/13 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs 71 024 t/u ordering information part number package access time temp. range status gs71024t-8 100-pin tqfp 8 ns commercial gs71024t-10 100-pin tqfp 10 ns commercial gs71024t-12 100-pin tqfp 12 ns commercial gs71024t-15 100-pin tqfp 15 ns commercial gs71024t-8i 100-pin tqfp 8 ns industrial not available gs71024t-10i 100-pin tqfp 10 ns industrial gs71024t-12i 100-pin tqfp 12 ns industrial gs71024t-15i 100-pin tqfp 15 ns industrial gs71024u-8 6 mm x 8 mm fine pitch bga 8 ns commercial gs71024u-10 6 mm x 8 mm fine pitch bga 10 ns commercial gs71024u-12 6 mm x 8 mm fine pitch bga 12 ns commercial gs71024u-15 6 mm x 8 mm fine pitch bga 15 ns commercial gs71024u-8i 6 mm x 8 mm fine pitch bga 8 ns industrial not available gs71024u-10i 6 mm x 8 mm fine pitch bga 10 ns industrial gs71024u-12i 6 mm x 8 mm fine pitch bga 12 ns industrial gs71024u-15i 6 mm x 8 mm fine pitch bga 15 ns industrial * customers requiring tape and reel should add the character ?t? to the end of the part number. for example: gs 71 024 t/u -12t.
rev: 1.03 11/2000 13/13 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs 71 024 t/u revision history rev. code: old; new types of changes format or content page/revisions/reason gs 71 024rev 2:17pm, 4/8/ 1999; 1.00a5/1999 format/typos ? document changed subscripts to small caps. ? 1/features: changed tp to t. ? document/replaced ?micro? with ?fine pitch?. content ? ordering information/added tape and reel note/ enhancement ? pin description/changed a0 - a14 to a0 - a15/correction ? page 1/took out ?byte control? from features/correction ? 3/changed pin 97 from nc to ce2/correction ? gs 71 0241.00a5/1999; 1.01 8/1999b content 1. pin out/changed pin 89 from ck to nc/correction 2. pin out/changed pin 92 from nc to v/ s /correction 3. pin out/changed pin 93 from v/ s to x/ y /correction 4. pin out/changed pin 94 from x/ y to nc/correction gs 71 0241.01 8/1999c; 1.02 9/1999c content ? package diagram/changed dimension ?d max? from 20.1 to 22.1/correction gs 71 024rev 1.01 8 / 1999c;rev 1.0 2 2/2000d format ? gsi logo rev 1.0 2 2/2000d; 71024_r1_03 format and content ? updated format to comply with technical publications standards ? changed all v ssq to v ss and all v ddq to v dd in pinout on page 2 ? updated revision history (revision notes for 8/1999 incorrect)

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